1. Field of Invention
This invention relates to transversal filter equalizer methods, systems and program products. More particularly, the invention relates to methods, systems and program products for a programmable driver/equalizer with alterable analog Finite Impulse Response (FIR) filter having low intersymbol interference and constant peak amplitude independent of coefficient settings.
2. Description of Prior Art
In transmission systems, particularly those for serial links in backplanes, there exists a need to equalize the link from the perspective of reducing the differences between long run lengths of data and short run lengths of data. The frequency content of the data will vary with the data itself. As a result, InterSymbol Interference (ISI) results which manifests itself in the distortion of the data signal and interference of one bit with one or more subsequent bits. Equalization when performed at the transmit end is normally specific to a given transmit medium, and the inherent parameters associations with the transmit media. The problem can be mitigated by properly filtering the pulses prior to transmission to compensate for the impairment in the transmission system. The pre-filtering has the effect in systems for serial links of equalizing the link from the perspective of reducing the differences between long run lengths of data and short run lengths of data. What is needed in the art is a driver with an alterable analog Finite Impulse Response (FIR) filter for serial links to enable the equalization in the system to adapt to a variety of transmission media and impairment. A constant peak amplitude is desirable in serial links so that a given link type may be equalized for a variety of attenuation amounts while preserving freedom to set different equalizations.
Prior art related to transversal filter equalizers includes the following:
U.S. Pat. No. 4,607,241 issued Aug. 19, 1986, discloses a transversal filter equalizer using a tapped delay line in which symmetrically located pairs of tap signals are combined by means of adders and subtracters, to provide partial output signals which are separately controlled in amplitude and phase. The partial output signals, which have no D.C. component, are then summed with a partial signal derived from a center tap reference signal to reinsert the D.C. component and to provide the equalized output signal.
U.S. Pat. No. 5,479,363 issued Dec. 26, 1995, discloses a programmable digital finite impulse response filter and correlator which includes a p-tap consisting of a switchable unit-delay and a two-non-zero-digital partial product generator and adder. The combination of several p-taps, made possible by the switchable delay, allows for the efficient implementation of coefficients with more than two non-zero digits. The switchable unit-delay not only allows the programming of the number of taps and the specific tap coefficient values, it provides a capability for programming the optimal allocation of hardware resources to each filter tap.
A publication entitled “A High Speed Programmable Digital FIR Filter ” by J. B. Evans et al., 1990 International Conference on Acoustics, Speech and Signal Processing, Albuquerque, N.Mex., Apr. 3-6, 1990, discloses the use of powers-of-two quantized coefficients which allows the simplification of circuitry required for the implementation of FIR filters by replacing multiplication with a limited number of shift-and-add operations with the corresponding increase in speed and area efficiency.
A publication entitled “A 100 MHz 40-Tap Programmable FIR Filter Chip” by M. Halamian et al., IEEE International Symposium on Circuits & Systems (23rd 1990: New Orleans, La., May 1-3, 1990) discloses a 40-tap filter in which each tap consists of a 12×10 bit multiplier, a 26-bit adder and a 10-bit adder along with 5 registers. Registers R1 and R2 represent the pipeline registers inserted in a computation path to achieve a desired throughput. Registers 3 and 4 are placed in a return path for the purpose of handling the symmetric filtering mode. Register 5 is used to hold the partial sums needed for the FIR filtering operation. The input signal is broadcast to all 40-taps in parallel. The 40th stage is fed back through control logic to the input of the next stage. The return path in the cascaded structure forms a chain of registers that feeds the delayed version of the input signal to the input adder of each module of each tap for the purposes of implementing a symmetric/anti-symmetric filter.
None of the prior art discloses a driver equalizer in which coefficients of the equalizer filter are alterable in arbitrarily small increments (analog), matched to each other, and a constant peak amplitude, independent of coefficient selection enabling power settings to be used for all possible coefficient possibilities whereby the output of the driver is matched to the inverse of transmission line frequency response regardless of transmission media type.